1. Field
This disclosure generally relates to computer networking. More specifically, this disclosure relates to methods and apparatuses for receiving and handling data packets on a computer system with multiple hardware threads.
2. Related Art
A typical computer system communicates over a computer network using a network interface unit (NIU) that facilitates transmission and reception of data packets. High-performance NIUs usually support direct memory access (DMA) operations. A descriptor ring is typically used to manage memory buffers for storing received packets. A driver allocates memory buffers for storing received packets, and posts descriptors for the memory buffers on the descriptor ring. The NIU fills the memory buffers as packets are received and notifies the driver when the packets are ready to be consumed. The NIU also notifies the driver when a memory buffer is ready to be recycled.
It is generally desirable to improve the performance of the receive path in multi-processor systems. Unfortunately, conventional buffer management techniques that use descriptor rings are designed to support a single hardware thread. Hence, using a conventional buffer management technique in a multi-processor system which supports multiple hardware threads can cause severe performance degradation. Note that using a separate descriptor ring for each hardware thread is not desirable because it can waste memory resources.